Rahul Ramachandran
Electrical Engineering Student @UNSW
Passionate about building high-performance digital systems - with a focus on embedded systems and FPGAs.
RR

Languages

VHDL
C++
Verilog
C
Python

Software

Vivado
Vitis
STM32CubeIDE
Git
KiCAD
LTSpice
MATLAB
Altium
PSpice
Maple
My Projects

A curated collection of my engineering work across FPGA design, embedded systems and systems programming

Logic Gate Learner

Hardware accelerator implemented on an Arty A7 100T for a custom neural network design from scratch in Python, trained for MNIST digit recognition.

Verilog
Python

Lightweight HTTP Server

Built a lightweight HTTP/1.1 server from scratch in C++ using raw POSIX sockets and a custom thread pool. Designed for concurrency, clean resource ownership (RAII), and gzip compression support.

C++

RV32I Softcore CPU

Designed and implemented a custom 32-bit RISC-V CPU from scratch in VHDL. Verified the design on my Arty A7-100T FPGA board

VHDL

Real-Time Sign-Language Translation Glove

Co-developed a wearable glove with flex sensors, IMU, and heart-rate monitoring for real-time Auslan (Australian Sign Language) recognition.

C++
Python

Battery Management System

Custom STM32-based BMS tailored for single-cell lithium-ion applications. Features include voltage monitoring, fault detection, and UART-based diagnostics.

C

CHV003 GPIO Driver

Custom GPIO driver for the CH32V003 microcontroller, designed for efficient pin control, interrupts, and low-level hardware access.

C
Contact

Get in Touch

Interested in collaborating or working on a project? Feel free to reach out via email